The Low Temperature Poly-silicon (LTPS) technology is the manufacture technology of the new generation TFT substrate. The response speed of the LTPS display is faster and possesses advantages of high brightness, high resolution and low electrical power consumption. The Poly-silicon (Poly-Si) possesses excellent electrical property, and the better drive ability to the Active-Matrix Organic Light Emitting Diode (AMOLED). Thus, the AMOLED display back plate based on the Low Temperature Poly-silicon technology has been widely utilized at present.
The Excimer Laser Annealing (ELA) technology is the key skill in the LTPS manufacture process. The skill is to utilize the transient pulses of the laser to irradiate on the surface of the amorphous silicon layer to be melted and recrystallized to form the Low Temperature Poly-silicon.
The AMOLED driving requires a drive TFT and a display TFT. The drive TFT demands larger lattice and thus higher electron mobility is required. The display TFT needs efficient electron mobility and uniformity of the electrical current. Accordingly, the OLED element can uniformly illuminate.
Please refer to FIG. 1 to FIG. 4, which show diagrams of a manufacture method of a Low Temperature Poly-silicon TFT substrate according to prior art. The method comprises:
step 1, providing a substrate 100, and the substrate 100 comprises a drive area and a display area; depositing a buffer layer 200 on the substrate 100, and depositing an amorphous silicon layer 300 on the buffer layer 200;
step 2, implementing an Excimer Laser Annealing process to the amorphous silicon layer 300 to make the amorphous silicon layer 300 to be crystallized and converted to be a polysilicon layer 400 after an Excimer Laser Annealing pretreatment;
step 3, patterning the polysilicon layer 400 to form a first polysilicon section 410 in the driving area, and a second polysilicon section 420 in the display area;
step 4, sequentially forming a gate isolation layer 500, a first gate 510 and a second gate 520 respectively located in the driving area and the display area on the buffer layer 200, the first polysilicon section 410 and the second polysilicon section 420, an interlayer insulation layer 600 located on the gate isolation layer 500, the first gate 510 and the second gate 520, and a first source/the first drain 710 and a second source/the second drain 720 respectively located in the driving area and the display area;
A first via 610 and a second via 620 are respectively formed in the gate isolation layer 400 and the interlayer insulation layer 600 correspondingly above the first polysilicon section 410 and the second polysilicon section 420; the first source/the first drain 710 and the second source/the second drain 720 respectively contact with the first polysilicon section 410 and the second polysilicon section 420 through the first via 610 and the second via 620.
However, the ELA crystallization technology according to prior art cannot achieve effective control to the uniformity of the lattices and the crystallization direction of the lattices. The distribution of crystallization condition in the entire substrate is extremely nonuniform and results in that the display effect is not uniform.
Consequently, there is a need to provide a manufacture method of a Low Temperature Poly-silicon TFT substrate and a Low Temperature Poly-silicon TFT substrate for solving the aforesaid problems.